FIG. 10 is a diagram illustrating the bus constitution adopted in the prior art in a system that requests real time operation for data input/output.
As shown in FIG. 10, system 100 is roughly divided into high-speed transfer part 101 that requires real time operation, and control processing part 102 that executes various controls and treatments by means of CPU control parallel to said high-speed transfer. If the real time operation requirement cannot be met because the output speed of data is lower than the input speed of data for the overall system at the data quantity (data transfer bandwidth) that can be transferred in unit time of the bus (known as CPU bus or system bus) owned by control processing part 102, high-speed transfer part 101 that allows real time data transfer works to meet the demand.
In said high-speed transfer part 101, input interface 102, burst data traffic control part 103, and output interface 104 are inserted in data high-speed transfer path (real time data bus) 105. High-speed memory 106 is connected to burst data traffic control part 103, and, under its control, high-speed data input/output can be performed via the input/output ports with a large bandwidth. Said burst data traffic control part 103 is connected to data processor 107 in control processing part 102, and, by means of this part, it is possible to fetch the data directly without going through CPU 109. Said data processor 107 performs the necessary treatment for the data read from high-speed memory 106 without degrading the real time property, and it outputs the processed data to burst data traffic control part 103.
In addition to high-speed treatment for image data, etc., performed by data processor 107, control processing part 102 mainly performs treatment of the control system, and it has CPU 109 and DMA (Direct Memory Access) control part 110 as the master devices connected to CPU bus 108. Said control processing part 102 has (low-speed) memory 111 and various peripheral devices (peripherals 0-3) 112 as slave devices connected to CPU 108.
For a system that processes images, as explained above, it is necessary to meet the requirement of real time data transfer when data are continuously input and data are continuously output at the same speed. However, when a high-speed bus constitution extending to the treatment of the system control unit is formed, all the master devices and slave devices connected to the bus are required to have a high-speed treatment ability, so the system becomes very expensive. Also, in the constitution of the CPU bus only, when the CPU bus is used by a master device (CPU 109, DMA control part 110, etc.), it cannot be used by other master devices (such as data processor 107). Consequently, this phenomenon hampers the treatment of the high-speed transferred data. As a result, as shown in FIG. 10, bus (CPU bus) 108 of the system control unit is formed with the necessary data transfer bandwidth, and high-speed transfer part 101 having real time data bus 105 with a data transfer bandwidth larger than said necessary data transfer bandwidth is set separately.
A problem of this bus constitution is that it is impossible to easily change the transfer path of data in two transfer systems. That is, when transfer is necessary between the two transfer systems via a CPU bus with a small data transfer bandwidth, the bus constitution should be redesigned from the initial bus constitution, or it may be necessary to have a special I/F bus that does not go through CPU bus 108 upon the request of the system as shown in the Figure. In the example of constitution shown in FIG. 10, specific I/F buses 113A, 113B, 113C, 113D are connected between CPU 109, memory 111, a peripheral device (Peripheral 0), a peripheral device (Peripheral 1) and burst data traffic control part 103.
In this case, for the slave devices using the data in the high-speed memory via the specific I/F bus, that is, memory 111, a peripheral device (Peripheral 0) or a peripheral device (Peripheral 1), a DMA function is necessary, and the structure of each slave device is complicated.
Also, change of the clock is necessary between said slave devices and high-speed transfer part 101 that handles data at a high speed, so the structure is complicated.
In addition, by adding the functions of the slave devices that meet said requirement, the logic is increased, and the device size increases.
As explained above, each time the system is changed, it is necessary to reconstruct the bus, it is impossible to reuse the two transfer system blocks, and the overall constitution is complicated each time the system is changed.
Although this problem does not directly cause problems in function, its development nevertheless requires significant resources, that is, many man-hours are required for specifications determination, design, simulation, and evaluation. Also, the overall system is prone to becoming complicated. As a result, problems are caused and a risk for requirement of redesign may occur. Also, realization of a low price becomes harder.
On the other hand, as a structure that allows easy adjustment of the number of master devices and slave devices and easy change of the type, an interconnection bus constitution exists (also known as multi-layer or central resource constitution).
FIG. 11 is a simplified diagram illustrating the constitution of a system that adopts the interconnection bus constitution. In FIG. 11, only the data flow is shown, while the control signals are not shown.
As shown in FIG. 11, system 200 has interconnection bus controller 201 (interconnect bus controller), four master devices MS0-MS3 connected to interconnection bus controller 201, and four slave devices SV0-SV3 connected to interconnection bus controller 201.
The interconnection bus controller 201 has interconnection bus BS, and four master interfaces (to be referred to hereinafter as master I/F) 21-0 through 21-3 connected for interconnection to bus BS to the side of the master devices. Also, four slave interfaces (to be referred to hereinafter as slave I/F) 22-0 through 22-3 are connected to the slave device side of interconnection bus BS. The master I/Fs 21-0 through 21-3 are each connected to one master device, and control the flow of data and control signals with respect to the master device. Similarly, slave I/Fs 22-0 through 22-3 are each connected to one corresponding slave device, and control the flow of the data and control signals with respect to the slave device. For the master I/Fs 21-0 through 21-3 as shown in FIG. 11, data are input from different slave devices, and selector 211 selects and outputs one of them. Also, slave I/Fs 22-0 through 22-3 have data input from different master devices, and selector 221 selects and outputs one of them.
In interconnection bus BS, each master I/F and slave I/F has an independent bus for transmission, and sends a data signal with respect to its unique bus for transmission. Also, each master I/F and slave I/F is connected to the transmission bus of all the other slave I/Fs and master I/Fs, and a data signal is received from the one transmission bus selected by the selector.
In the following, an explanation will be presented in detail regarding an example of operation in which a data signal is transmitted from a master device to a slave device upon request from the master device.
At first, master devices MS0-MS3 send the address (ADRS) that specifies the slave device for data transmission to the corresponding master I/Fs. Said master I/Fs 21-0 through 21-3 decode the address sent from the corresponding master devices, and output the access request (request signal) to a slave I/F. This request signal is transmitted to the slave I/F via interconnection bus BS.
When slave I/Fs 22-0 through 22-3 receive several signals from master I/Fs, one master I/F is specified according to the priority order allotted to the master devices, and only the grant signal is sent to said master I/F. If there is one request signal, the slave I/F sends the master I/F grant signal of the transmitting source of the request signal.
On the other hand, if a grant signal does not come from the slave I/F that requests access, master I/Fs 21-0 through 21-3 output a standby signal to the connected master device. When a grant signal is received from the slave I/F that requires access, the master I/F outputs the grant signal to the master device. The master device that receives the grant signal outputs the prescribed data signal via the master I/F.
For slave I/Fs 22-0 through 22-3, from several input signals, the data signal from the granted master device is selected by selector 221, and it is output to the connected slave device.
As explained above, a data signal is sent from the master device to the slave device. In the reverse case, slave I/Fs 22-0 through 22-3 output a data signal from the connected slave device, and selector 211 in master I/F selects the data signal from the slave device that requests access, and outputs it to the connected master device.
In the aforementioned interconnection bus constitution, when a slave device is to be added, an unused address is allotted to the slave device, and said slave device is simply connected to an unused (or newly added) slave I/F. Consequently, in this system using an interconnection bus, it is easy to change the system constitution without changing the interconnection bus constitution itself. This is an advantage.
However, in the interconnection constitution, the transfer ability of all the master and slave parts depends on the data transfer bandwidth and operation frequency of the bus. Consequently, in a system that requires a real time property, it is necessary to increase the data transfer ability of the bus itself to meet the demand for the real time data transfer. However, when such high data transfer ability is equipped, the price of the bus constitution rises, and the operation frequency rises, so the operation is likely to be unstable. In addition, such a high data transfer ability becomes useless overhead for the other slave devices that do not require real time operation. In some cases, it is also necessary to change the clock.
In addition, there are other problems in the interconnection bus constitution. As one such problem, one slave device is used for one master device. In this case, the other master devices cannot access said slave device. That is, when a master device having high priority uses a certain slave device, the other master devices with a lower priority may be unable to access the slave device.